Solutions providers face many challenges in creating devices that allow radio frequency (RF) connectivity for multiple communication schemes to operate successfully on a single silicon die. Transmission and reception schemes can conflict, forcing innovations in order for on-chip RF functions to coexist or be multiplexed. Sharing the same antenna among different technologies compounds these conflicts and increases the need for enhanced design. Signal interference between different RF technologies can cause difficulties for handset users, including reduced call reliability and even dropped connections.
RF circuit in a multiple radio SoC is prone to interference. It is found that a digital circuit in the SoC significantly contributes to the interference. If any of the harmonics of the frequencies of a digital clock signal (of the digital circuit) lie in any of the RF frequency band of interest, it will interfere with the RF signal and the circuit may not function as expected.
Several existing techniques, for example, frequency planning approach and clock dither technique try to solve this problem of interference. In frequency planning approach a high frequency of operation is selected which does not fall into the frequency band of operation. However, in this approach, effective throughput of the system is affected. Therefore to achieve the same throughput, there would be a need to use random clock swallowing. Timing and area are also impacted due to the increase in clock frequency. In clock dither technique, a jitter in the clock is introduced in order to spread the spectrum of the power profile. However, in clock dither technique, extra complexity is added to the circuit. Also this technique cannot be directly used for clocking the external interfaces, which would otherwise lead to additional complexity in timing.